1. Field of Invention
The invention relates to a method for pattern etching a substrate, and more particularly to a method for pattern etching a substrate while reducing the effects of micro-loading and feature roughness.
2. Description of Related Art
Typically, during fabrication of integrated circuits (ICs), semiconductor production equipment utilize a (dry) plasma etch process to remove or etch material along fine lines or within vias or contacts patterned on a semiconductor substrate. The success of the plasma etch process requires that the etch chemistry includes chemical reactants suitable for selectively etching one material while substantially not etching another material.
For example, on a semiconductor substrate, a pattern formed in a protective mask layer can be transferred to an underlying layer of a selected material utilizing a plasma etching process. The protective mask layer can comprise a radiation-sensitive layer, such as a photo-resist layer, having a pattern formed therein using a lithographic process.
In order to pattern finer features in the lithographic layer using conventional lithography techniques, multi-layer masks can be implemented. For example, the multi-layer mask may include a bilayer mask or trilayer mask including one or more soft mask layers, or one or more hard mask layers, or a combination thereof. With the inclusion of a second or third layer, the uppermost lithographic layer may be thinner than the thickness customarily chosen to withstand the subsequent dry etching process(es) and, therefore, using conventional lithography techniques, finer features may be formed in the thinner lithographic layer. Thereafter, the finer feature formed in the lithographic layer may be transferred to the underlying second or third layers using a dry development process, such as a dry etching process.
Once the pattern is established in the multi-layer mask, the pattern is transferred to the underlying layers using one or more etching processes. Examples of such an etching process include reactive ion etching (RIE), which is in essence an ion activated chemical etching process. However, although RIE has been in use for decades, its maturity is accompanied by several issues including, among other things, feature-shape loading effects (i.e., micro-loading) and critical dimension (CD) control. A loading effect is generally used to describe an etching process having an etch rate that depends upon the exposed area. Local variations in the pattern density of the pattern being transferred using the etching process can cause local variations in the etch rate due to local depletion of the reactive species and this effect is referred to as micro-loading. It is essential that the micro-loading effect is reduced in order to mitigate RIE lag. Moreover, as pattern feature dimensions become finer, RIE lag worsens.
Additionally, it is essential that a critical dimension (CD) for the mask layer is preserved during pattern transfer such that the CD bias is minimal, i.e., the CD bias is the difference between the initial CD for the pattern in the mask layer and the final CD for the pattern in the underlying layer(s). Further, if a CD bias is unavoidable, it is essential that the CD bias is uniformly maintained across the substrate. Further yet, if a CD bias is unavoidable, it is essential that the offset in CD bias between dense features (e.g., closely spaced features) and isolated features (e.g., widely spaced features) is minimal.
Furthermore, during pattern transfer, undulations or variations in the edge profile of the pattern in the mask layer as well as variations in pattern dimension, can be propagated in to the underlying layers. These undulations or variations may be observed as edge roughness or line edge roughness (LER) in some instances, or as pitting in other instances. Edge roughness may arise due to damage to the layer of radiation-sensitive material. During the application of the radiation-sensitive material, the post-application bake (PAB), the exposure step, the post-exposure bake (PEB), or the wet developing step, or any combination thereof, the radiation-sensitive material may be damaged. Moreover, damage may occur during the initial phases of the ARC layer etch, hard mask etch, or thin film etch. Pitting may arise when performing pattern transfer in a porous material, such as porous low dielectric constant (low-k) materials or porous ultra-low-k materials.